The original contract
8086
1978
01 · Lineage
The architecture stayed.
The machine beneath it did not.
Move the time cursor. Each stop separates three things that are often muddled together: the software-visible instruction set, the hidden microarchitecture that executes it, and the physical product that contains both.
Generation
8086 · 1978
Fetch and execute become two overlapping jobs.
What changed
New words in the language
The next bottleneck
A logarithmic journey
Transistor budget
Linear bars would make the 8086 vanish. Height here is logarithmic; labels retain the honest count.
Architecture
The contract software can observe: registers, flags, address translation, instruction encodings and exceptions. A Pentium 4 still promises to execute old 8086 code, subject to mode and platform constraints.
Microarchitecture
The private method used to honour that contract: queue, pipeline, dual issue, micro-operations, renaming, predictors and caches. It may change completely while the bytes remain valid.
Implementation
Process node, transistor budget, package, clocks, bus and cache sizes. “Pentium III” spans implementations whose cache and manufacturing details differ while sharing a core lineage.
02 · Decode
A language with no spaces
and forty years of footnotes.
x86 instructions are variable-length records embedded back-to-back in memory. The decoder must discover the boundary while interpreting prefixes, opcode maps, addressing bytes, displacement and immediate data.
Byte laboratory
audited subset
Instruction decoder
Spaces and commas are optional. The lab recognises common integer, MMX, SSE and SSE2 examples; unknown opcodes are still split into structural fields.
Reading
MOV AX, word ptr [BP + 4]
General form
The expanding grammar
Not every instruction contains every field. That optionality makes the encoding compact—and makes instruction boundaries real work.
0–4Prefixeslock · repeat · segment · size
1–2+Opcodeprimary map or escaped map
0–1ModR/Mmode · register · r/m
0–1SIBscale · index · base
0–4Displacementaddress constant
0–4+Immediateliteral operand
Compact CISC
One-byte opcodes do a remarkable amount of work. Direction and width bits are sometimes embedded in the opcode itself; ModR/M selects register and memory forms.
Escape and override
The 386 uses 0F as a second opcode map, adds FS/GS, 66/67 size overrides and SIB. Sixteen- and thirty-two-bit code share one grammar.
Prefixes become selectors
MMX, SSE and SSE2 reuse opcode maps. Legacy bytes such as 66, F2 and F3 can become mandatory parts of a new vector opcode rather than ordinary overrides.
03 · Pipeline
Latency is how long one takes.
Throughput is how often another may start.
Run the same stream through several conceptual machines. A pipeline does not make an individual dependent chain magically shorter; it overlaps different instructions so completed work can emerge more often.
Clock0
Current ideaThe bus fetches ahead into a six-byte queue.
This is an explanatory schedule, not a transistor-level simulator.
front end
execute
architectural completion
flushed wrong path
Fill
The first result still traverses the machine. A deeper pipeline spends more clocks before steady-state throughput appears.
Flow
Once full, independent instructions occupy different stages. The 486 aims to begin a simple instruction each clock.
Flush
A wrong branch invalidates younger work. The deeper the speculative runway, the more useful work must be rebuilt.
04 · Superscalar
Two-wide is not the same as
two instructions every clock.
Compare a scalar pipeline, Pentium's in-order U/V pairing and a simplified P6-style out-of-order engine. The original program order is identical; what changes is who may pass whom inside the core.
Model
Pentium: pair in order
The V pipe may accept only a suitable companion. A blocked old instruction blocks younger ones, even when they are independent.
Cycles0
Instructions0
IPC0.00
Architectural order
12345
The program observes this order. Exceptions must describe a precise point in it.
Execution order inside P6
14523
Ready operations may execute early, but the reorder buffer retires their results as 1, 2, 3, 4, 5.
05 · Branches
The processor must choose a future
before the present has finished.
Train four predictor ideas on repeatable patterns. The state machines are real concepts; the table sizes and product penalties are intentionally pedagogical unless a product source says otherwise.
Predictor state
00strong N
01weak N
10weak T
11strong T
Predict taken; one contrary result only weakens the belief.
Branches0
Correct0
Accuracy—
Lost clocks0
Prediction: TWaiting
No prediction
Sequential prefetch continues until a taken transfer proves the next bytes useless. The queue is discarded and refilled at the target.
Remember targets
A branch target buffer lets the front end recognise a branch at fetch time and pursue a remembered path early.
Speculate deeply
Prediction now feeds an out-of-order window. Correct guesses expose more parallelism; wrong guesses discard a larger cloud of µops.
Trace the predicted path
The trace cache stores decoded µops in execution order across taken branches. Prediction helps decide which trace is useful.
06 · Cache
The fastest memory is the byte
you did not have to fetch.
Split an address into tag, set and offset, then generate access patterns. Cache geometry is exact arithmetic; the latency numbers are a teaching model because real systems include buses, write policy, TLBs, banks and multiple cache levels.
Tag0x418 bits
Set0xF37 bits
Offset0x44 bits
8 KiB ÷ (16 B × 4 ways) = 128 sets
Hits0
Misses0
Hit rate—
Modelled AMAT—
Outside the core
No general on-chip cache in these flagship parts. Boards could add external cache; memory and bus timing remained conspicuous.
0One nearby store
An 8 KiB unified on-chip cache supplies both instructions and data and makes the five-stage pipeline much less dependent on the motherboard.
8KSplit the traffic
Separate 8 KiB instruction and 8 KiB data caches let the dual pipelines fetch code and access data without fighting for one L1 port.
8+8Cache decoded work
The trace cache holds roughly 12K µops rather than ordinary instruction bytes; an 8 KiB data L1 and 256 KiB L2 serve the launch part.
µops07 · Cycles
One number stopped being enough.
That is the story.
Early manuals can quote an instruction in clocks under explicit assumptions. Superscalar and out-of-order cores need at least latency, reciprocal throughput, µop count, dependency shape, prediction and cache state.
Teaching model
Build a thousand-instruction workload
This deliberately simple model exposes interactions; it is not a benchmark or product performance claim.
—modelled clocks
Latency
Clocks from an operation starting until a dependent operation may consume its result.
Throughput
How often another independent operation of that class may begin once the machine is flowing.
µops
The number and kind of internal operations a visible x86 instruction becomes. One mnemonic may occupy several resources.
Retirement
The rate at which completed speculative work becomes architectural history in original program order.
08 · Sources
What the diagrams claim—
and what they deliberately do not.
The factual backbone is Intel's period documentation. The interactive models simplify implementation details to make one mechanism legible at a time, and mark those simplifications rather than smuggling them in as product facts.
Documented fact
Dates, transistor counts, address widths, cache headlines, instruction additions and named microarchitecture features are tied to manufacturer manuals or Intel's historical material.
Explanatory model
Animated schedules, branch table sizes, generic cache penalties and workload totals are purpose-built models. They show causality, not a cycle-accurate netlist.
Product variation
A family name spans steppings and products. Pentium MMX is not the 1993 launch Pentium; Coppermine differs from Katmai; later Pentium 4 cores deepen and change the launch design.
Primary shelf
Manuals and technical announcements
PDF links open the original scanned manuals; HTML links open Intel's archived technical material.
Caveat A
“Pipeline depth” is a counting convention.
Manufacturers and analysts may count different boundaries. This site uses Intel's launch description of a twenty-stage Pentium 4 pipeline and treats the shorter diagrams as conceptual stage groups.
Caveat B
Clock counts need assumptions.
Manual timings commonly assume prefetched instructions, aligned operands, cache hits or no bus wait states. The ledger repeats those assumptions and avoids comparing unlike numbers as if they were benchmark results.
Caveat C
Predictor internals are not all public.
The predictor lab teaches static, last-outcome, two-bit and history-based mechanisms. It does not assert that its tiny tables exactly reproduce a particular commercial part.
Caveat D
Compatibility is not identity.
Later processors preserve a great deal of earlier software-visible behaviour, but modes, undefined flags, timing, undocumented instructions, platform hardware and errata prevent “the same processor, only faster” from being literally true.
The deepest continuity is not a pipeline or cache.